1. Technical Field
This disclosure relates to switching voltage regulators and more particularly to an architecture of constant-on-time multi-phase switching voltage regulator.
2. Description of the Related Art
CPU for PCs, WORKSTATIONS and SERVERS typically need very sophisticated supply control mechanisms. These power supplies must typically meet high precision requirements both in stand-by conditions as well as in conditions of load transients. These requirements led to identify the well known architectures of multi-phase buck regulators as the most appropriate to this objective.
In order to effectively respond to very fast and large load transients (for example, in a CPU, up to 100 A or more in 50 ns) these converters typically employ nonlinear controls that are enabled in presence of load transients and turn on simultaneously all the available phases for sustaining the output voltage. These nonlinear systems advantageously minimize the response time by reacting in an “aggressive” manner to the load transient. Moreover, the multi-phase topologies have control mechanisms for limiting the unbalancing of phase currents thus ensuring a thermal balancing and preventing excessive stresses of components of the power stage (power MOS and inductors).
FIG. 1 shows a N-phase constant-on-time switching voltage regulator driven by a VCO, that generates a clock with adjustable frequency corresponding to the voltage provided to the VCO. A state machine STATE MACHINE distributes the clock pulses to the phases by generating as many phase clock signals CKi by frequency division of the clock signal CLOCK. The blocks TON_GEN_i are input with the respective phase clock signals CKi and with the sum between the output voltage VOUT and a voltage VCSi representing the unbalancing of each respective phase and determine, according to well known techniques, the respective phase duty-cycles DUTYi of the respective PWM voltages that supply the phase windings.
In order to make the output voltage VOUT track the reference voltage VREF and to nullify the error in steady-state conditions, an integrating network ZF is connected between the terminals COMP and FB of the switching regulator and a feedback impedance ZFB is connected between the output terminal OUT and the feedback terminal FB.
In constant-on-time multi-phase switching voltage regulators, when the current absorbed by the supplied load decreases, it is useful to reduce the number of active phases, for example from a number N to a number N-X, in order to reduce power dissipation and thus to increase the efficiency of the voltage regulator. This is done by reducing the voltage inputting the VCO, as shown in FIG. 2, in order to reduce the frequency of the clock signal provided to the state machine.
When the number of active phases is reduced (or increased), the voltage provided to the VCO decreases (increases) when the integrating network ZF discharges (charges) itself, that in the shown example is a RF-CF network, with a time constant determined by the capacitance CF and the resistance RF. As a consequence, the voltage provided to the VCO could vary slowly and cause out of specifications undershoots (overshoots) of the output regulated voltage VOUT.